1. Field of the Invention
The present invention relates to a substrate voltage generator for applying a prescribed bias voltage to a semiconductor substrate and particularly to a substrate voltage generator and a method therefor in a semiconductor device having an internal voltage down converter for lowering an external power supply voltage, thereby generating an internal stepped-down power supply voltage.
2. Description of the Background Art
Recently, 4 M (mega) bit static random access memories (SRAMs) and 16 M (mega) bit dynamic random access memories (RAMs) utilizing micro-lithography of 0.5 .mu.m level have been developed and made public. It is pointed out that if a short channel MOS (insulated gate field effect) transistor of a gate length of less than 0.6 .mu.m is operated by a power supply voltage 5 V in the same manner as in a MOS transistor of a gate length of about 1 .mu.m to 0.8 .mu.m used in a 4 M bit DRAM or the like, transistor characteristics are deteriorated considerably due to time dependent dielectric breakdown of a gate insulating film or the like, causing reliability to be lowered.
In order to use a short channel MOS transistor having a gate length of 0.5 .mu.m not causing such deterioration of transistor characteristics, it may be considered to change the power supply voltage from 5 V to 3.3 V for example. However, in view of adaptability to the 5 V power supply system widely used conventionally, a problem is involved in the change of the power supply voltage. Therefore, there has been proposed a system of operating an internal circuit of a semiconductor memory device by a stepped-down voltage of e.g. 3.3 V while maintaining the external power supply voltage at 5 V as in the prior art.
FIG. 1 is a functional block diagram of a conventional semiconductor device having an internal voltage down converter. Referring to FIG. 1, the semiconductor device includes a function circuit 101 formed by a memory for example for performing a prescribed function, and an input/output circuit 102 for transfer of data between the function circuit 101 and an external unit. The semiconductor device further includes an internal voltage down converter 103 for lowering an externally applied power supply voltage Vocc and generating a prescribed internal power supply voltage Vicc, and a substrate voltage generator (V.sub.BB generator) 104 responsive to the external power supply voltage Vocc for generating a prescribed bias voltage and applying the same to a semiconductor substrate 100.
The semiconductor device shown in FIG. 1 contains the internal voltage down converter 103 integrated on the semiconductor substrate 100, and the external power supply voltage Vocc is converted to be stepped down by the internal voltage down converter 103, whereby the prescribed internal power supply voltage Vicc is generated. In some cases, the prescribed internal power supply voltage Vicc is supplied to only the function circuit 101, and in some cases, it is supplied to both the function circuit 101 and the input/output circuit 102.
FIG. 2 is a block diagram of the internal voltage down converter shown in FIG. 1, which is disclosed for example by Furuyama et al. in IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 3, June, 1987, pp. 437-441. Referring to FIG. 2, the internal voltage down converter 103 includes: a reference voltage generating circuit 110 for generating a prescribed reference voltage Vref from the external power supply voltage Vocc; a differential amplifier 111 operating with the external power supply voltage Vocc as the operation power supply voltage for comparing the internal power supply voltage Vicc and the reference voltage Vref and generating a control signal (regulation signal) .phi..sub.x according to the result of the comparison; and an output circuit 112 responsive to the regulation signal .phi..sub.x from the differential amplifier 111 for receiving current from the external power supply voltage Vocc and generating the internal power supply voltage Vicc.
The differential amplifier 111 amplifies differentially the reference voltage Vref and the internal power supply voltage Vicc, thereby generating the regulation signal .phi..sub.x.
FIG. 3 is a diagram showing a specific construction of the internal voltage down converter shown in FIG. 2. Referring to FIG. 3, the reference voltage generating circuit 110 includes: three p channel MOS transistors P1, P2, P3 seriesly-connected between the external power supply voltage vocc and a second power supply voltage Vss as a ground potential for example; a p channel MOS transistor P4 connected between the external power supply voltage Vocc and a node N2 and receiving a potential of a node N1 at its gate; and a p channel MOS transistor P5 connected between the node N2 and the second power supply potential (referred to simply as the ground potential) Vss. The p channel MOS transistors P1 to P3 have their gates and drains connected together to function as a resistor, so that a voltage according to the on resistance thereof is supplied to the node N1. The p channel MOS transistor P4 receives the potential of the node N1 at its gate and has a resistance value according to the gate potential, and it transmits current from the external power supply voltage Vocc to the node N2. Those p channel MOS transistors P1 to P4 constitute a constant current load with respect to the p channel MOS transistor P5. Operation of this reference voltage generating circuit will be briefly described.
Now, let us assume a case in which the external power supply voltage Vocc is increased. In this case, a large amount of current flows into a path formed by the transistors P1 to P3, whereby the potential of the node N1 increases. In response to the increase of the potential of the node N1, the gate potential of the transistor P4 increases. Thus, the resistance value of the transistor P4 increases, making it difficult for current to flow in the transistor P4.
Conversely, if the external power supply voltage Vocc is decreased, the current flowing in the path formed by the transistors P1 to P3 becomes small. Thus, the potential of the node N1 is lowered and the resistance value of the transistor P4 becomes small, whereby current can easily flows through the transistor P4. The gate potential of the transistor P4 is regulated according to change in the external power supply voltage Vocc, whereby constant current always flows into the node N2 and the constant reference voltage Vref proportional to an absolute value of threshold voltage V.sub.TP of the transistor P5 appears at the node N2 (in the case where a plurality of transistors P5 are provided).
The differential amplifier 111 includes: a p channel MOS transistor P10 provided between the external power supply voltage Vocc and a node N3, and receiving a clock signal .phi.c at its gate; a p channel MOS transistor P11 provided between the external power supply voltage Vocc and the node N3 and having its gate connected to the ground potential Vss; a p channel MOS transistor P12 provided between the node N3 and a node N4 and receiving the reference voltage Vref at its gate; a p channel MOS transistor P13 provided between the nodes N3 and N5 and receiving the internal power supply voltage Vicc at its gate; an n channel MOS transistor NT1 provided between the node N4 and the ground potential Vss and having its gate connected to the node N5; and an n channel MOS transistor NT2 provided between the node N5 and the ground potential Vss and having its gate connected to the node N5 and the gate of the transistor NT1.
The transistor P10 has a relatively large current supplying capability, while the transistor P11 has a small current supplying capability to allow a very small current to flow. The control signal .phi.c is set to a logical low (L) level of an activated state during a period in which the function circuit 101 (as shown in FIG. 1) of the semiconductor device operates, and it is set to a logical high (H) level of an inactivated state during a period in which the internal circuit does not operate. Thus, the transistor P10 having the large current supplying capability is in a conducting state during the operation of the internal circuit to improve the response characteristics of a current mirror type amplifier (i.e., a circuit stage formed by the transistors P12, P13, NT1 and NT2), and only the transistor P11 is in a conducting state in the period of non-operation of the internal circuit, thereby reducing consumption current. Switching between the operation and non-operation of the internal circuit is effected in the following manner. For example, if the function circuit 101 is a memory, the control signal .phi.c is generated in response to a signal (e.g., a signal RAS) indicating whether a memory cycle is started or not.
The output circuit 112 is provided between the external power supply voltage Vocc and the internal power supply voltage line Vicc (a signal line and a signal transmitted thereon being shown by the same reference characters) and it includes a p channel MOS transistor P15 having its gate receiving the potential of the node N4 of the differential amplifier 111 as the regulation signal .phi..sub.x. Next, operations of the differential amplifier 111 and the output circuit 112 will be described.
Let us now assume that the internal power supply voltage Vicc becomes larger than the reference voltage Vref.
In this case, current flowing through the transistor P12 becomes larger than the current flowing through the transistor P13. The node N5 is connected to the gates of the transistors NT1 and NT2, and the transistors NT1 and NT2 constitute a current mirror circuit. The potential of the node N5 proportions to a value of the current flowing through the transistor P13. The larger the current flowing through the transistor P13 is, the higher the potential of the node N5 is, while the smaller the current is, the lower the potential is. The values of the current flowing in the transistors NT1 and NT2 become equal and accordingly the transistor NT1 does not allow the large current to sufficiently flow in the transistor P12, causing the potential of the node N4 to rise. In response to the rise of the potential of the node N4, namely, the regulation signal .phi..sub.x, the transistor T15 is brought into a shallow on state or an off state. As a result, the supply of the current from the external power supply voltage Vocc to the internal power supply voltage line Vicc is stopped or suppressed and the internal power supply voltage Vicc is lowered.
If the internal power supply voltage Vicc is smaller than the reference voltage Vref, the regulation signal .phi..sub.x is lowered oppositely to the above-mentioned case and the transistor P15 is brought into a conducting state or a deeply conducting state. Thus, a sufficient current is supplied from the external power supply voltage Vocc to the internal power supply voltage line Vicc, whereby the internal power supply voltage Vicc is increased.
As described above, the output level of the output circuit 112 is fed back to the differential amplifier 111, whereby the internal power supply Vicc is made constant. In this case, if there is a large delay in the feedback path of the differential amplifier 111, the output level of the output circuit 112, namely, the internal power supply voltage Vicc is brought into an oscillating state and a ripple component is superimposed onto the potential level. However, such oscillation of the output level of the output circuit is suppressed by sufficiently reducing the delay of feedback in the differential amplifier 111.
FIG. 4 is a graph showing a dependency characteristic of the internal power supply voltage Vicc generated by the internal voltage down converter shown in FIG. 3 on the external power supply voltage Vocc, as disclosed by Furuyama et al in the above-mentioned document. Referring to FIG. 4, the ordinate represents the internal power supply voltage Vicc and the abscissa represents the external power supply voltage Vocc. As seen from FIG. 4, the internal power supply voltage Vicc obtained by voltage conversion is maintained at a constant value of about 3.5 V set as the reference voltage Vref, in the range where the external power supply voltage Vocc is about 3.5 V or more. It is also seen that in the case of the external power supply voltage Vocc of 7 V, the internal power supply voltage Vicc is about 4 V.
If the semiconductor device is a memory device such as a DRAM, that is, if the function circuit in FIG. 1 includes a memory cell array, a substrate voltage generator 104 is provided in general as shown in FIG. 1. The substrate voltage generator 104 applies a prescribed negative potential to the substrate 100 if the semiconductor substrate 100 is a P type substrate. The purposes of applying such constant negative bias voltage to the P type semiconductor substrate are (1) to prevent injection of electrons into the substrate due to undershoot of a signal on a signal line, (2) to make stable the threshold voltage and operation characteristics by attenuation of the substrate effect of n channel MOS transistors, (3) to enhance the speed of operation of MOS transistors by reducing the stray capacitance involved in the junction capacitance between the substrate and an N type impurity layer, (4) to prevent generation of a parasitic MOS transistor by preventing formation of an inversion layer at an insulating film portion for element isolation (a field oxide film), (5) to prevent rise of the substrate potential due to a capacitance coupling between the power supply voltage line and the substrate, etc. The above-mentioned substrate effect is a phenomenon in which the threshold voltage and drain current etc. of an n channel MOS transistor formed on the surface of the semiconductor substrate vary according to the potential of the semiconductor substrate.
FIG. 5A shows a specific construction of a generally used substrate voltage generator. Referring to FIG. 5A, the substrate voltage generator 104 includes a ring oscillator 201 performing oscillation at a prescribed frequency, and a charge pump circuit 202 responsive to an oscillation signal from the ring oscillator 201 for injecting electrons into the semiconductor substrate and biasing the substrate at a prescribed negative potential (in the case of the semiconductor substrate of the P type). The ring oscillator 201 includes inverters I1, I2 . . . , Im cascade-connected by an odd number of stages. An output of the inverter Im of the final stage is connected to an input portion of the inverter Il of the first stage. The oscillation frequency of the ring oscillator 201 is determined mainly by the number of stages of the connected inverters, and the delay time in each of the inverters I1 to Im.
The charge pump circuit 202 includes a capacitor C1 having one electrode receiving an output signal f from the ring oscillator 201, an n channel MOS transistor NT11 having its gate and one electrode (drain) connected to the other electrode (node N20) of the capacitor C1, and the other conduction terminal connected to the ground potential Vss, and an n channel MOS transistor NT10 having one conduction terminal and a gate connected to the semiconductor substrate, and the other conduction terminal connected to the node N20. A connection point between the gate and one conduction terminal of the transistor NT10 is an output portion of the substrate bias voltage V.sub.BB. Next, operation of this substrate voltage generator will be described.
Let us now assume a case in which the threshold voltage of the MOS transistors NT10 and NT11 is Vtn, H level of the oscillation signal f is Vcc (i.e., the operation power supply voltage level), and L level is Vss. When the oscillation signal f rises to H level, a charge determined by a product of the capacitance of the capacitor C1 and the H level of the oscillation signal f is injected into the node N10 due to the capacitance coupling of the capacitor C1, whereby the potential of the node N10 rises. As a result, the transistor NT10 is brought into an off state and the transistor NT11 is brought into an on state. The increased potential of the node N20 is discharged by the transistor NT11 in the on state and the potential of the node N10 becomes equal to Vss+Vtn at the time of the first charge injecting operation.
Then, when the oscillation signal f falls to L level, the charge at the node N20 is drawn by the capacitance coupling of the capacitor C1, whereby the potential of the node N20 is lowered. At this time, the transistor NT10 is turned on and the transistor NT11 is turned off. Thus, the charge is drawn from the semiconductor substrate and the potential of the semiconductor substrate is slightly lowered.
By repeating the above-mentioned operation, the potential of the semiconductor substrate is gradually lowered by the drawal of the charge, namely, injection of electrons, and finally the potential attains the following negative potential: EQU 2.multidot.Vtn-Vcc.
Normally, the inverters I1 to Im included in the ring oscillator 201 as described above are formed by CMOS transistors (i.e., inverters including p channel MOS transistors PQ and N channel MOS transistors NQ) in the conventional structure as shown in FIG. 5B, and the external power supply voltage Vocc is used as the operation power supply voltage.
Now, the semiconductor device will be described by taking an example of a DRAM. It is possible to utilize two types of voltages, i.e., the external power supply voltage Vocc and the internal power supply voltage Vicc as the operation power supply voltage of the semiconductor device having the internal voltage down converter. Thus, either of the following voltages:
(1) the externally applied power supply voltage Vocc,
(2) the internal power supply voltage Vicc stepped-down by the internal voltage down converter can be used as the operation power supply voltage of the substrate voltage generating circuit.
A method of supplying the operation power supply voltage to the DRAM may be either of the following two methods.
A: Only a circuit of an input/output portion such as a data input/output buffer or an address buffer communicating signals with an external device is operated by the external power supply voltage Vocc, and other peripheral circuit and memory array portion are all operated by the internal power supply voltage Vicc. This is based on the following features. If the external device includes a MOS transistor operating with an operation power supply voltage of 5 V, the input/output circuit needs to input and output a signal having a swing of 5 V to 0 V, and in the internal circuit (including both the peripheral circuitry and the memory array portion), the use of the internal power supply voltage Vicc makes it possible to improve reliability and to attain a low power consumption characteristic and high-speed operability for the below described reasons.
The change amount of the internal power supply voltage Vicc is smaller than the change amount of the external power supply voltage Vocc. In addition, it is not necessary to give a large tolerance to operation timing in the semiconductor memory device. More specifically stated, the operation speed of the peripheral circuitry proportional to the driving capability of the transistor greatly depends on the power supply voltage, particularly the gate voltage. The circuit components such as the memory array and the sense amplifiers have a large load capacitance and accordingly the operation speed thereof is determined by a CR time constant of the load capacitance and the resistance, and have not so large voltage dependency as in the peripheral circuitry. Consequently, if the internal power supply voltage Vicc is used as the operation power supply voltage of the peripheral circuitry, it becomes possible to make the operation speed of the peripheral circuitry and that of the memory array portion coincide and to shorten the access time.
B: Only the memory array portion is operated by the internal power supply voltage Vicc stepped-down and other input/output circuits and peripheral circuitry are all operated by the external power supply voltage Vocc. This method is a method of designing a DRAM based on the conventionally used design method with as little change as possible. In the memory array portion, a reliability problem often occurs in memory cells due to a word line receiving the highest voltage and the drive circuit thereof, etc. and it is necessary to operate the memory array portion by the internal power supply voltage Vicc.
From the foregoing considerations, there are four combinations in the power supply voltage applying system for the DRAM and the voltage applying system for the substrate voltage generator. Discussions will be made in the following on the combinations of the respective power supply voltage applying systems.